As the scaling of the CMOS devices approaches its technological and fundamental limits, the replacement of silicon and its native oxide becomes one of the key challenges to sustain the continuous improvement of the IC performance. New semiconductors and dielectrics are at the heart of development of new and emerging high performance nanoelectronic devices. The key criteria for a successful implementation of a new generation of nanoelectronics products are: the cost per function reduction, the energy consumption of the components, the environmental life cycle of the materials, the reliability of the components over their lifetimes and the variability of components produced in a batch. For previous silicon-based systems, the standards for reliability and degradation are well established, and devices can maintain performance for over a decade. However, the latest 45 nm technology chips, featuring transistors shorter than 30 nm, start to suffer failures in less than five years and this trend will accelerate with the introduction of the 32 nm and 22 nm technology generations. This trend can be exacerbated further according to the 2009 edition of the ITRS since the future progress in performance scaling relies on new channel and gate dielectric materials. The first challenge listed in the section on Emerging Materials is “Integration of alternate channel materials with high performance”. Specific listed targets include “Demonstration of high mobility n and p channel alternate channel materials co-integrated with high-k dielectric” and “Demonstration of high mobility n and p channel carbon (graphene or carbon nanotubes) FETs with high on-off ratio co-integrated with high-k dielectric and low resistance contacts”. For devices based on new materials, we have very little understanding of the factors that will dominate degradation and reliability, and no coherent strategy to approach the problem. This means that the most promising route for the continuing development of nanoelectronics in Europe can be blocked if the nanoelectronics industry will have no confidence in reliability of devices based on these materials.
MORDRED integrates a multiscale atomistic modeling scheme with state-of-the-art experimental characterization to achieve a step change in the power of predictive modelling of reliability and degradation of contemporary and future CMOS devices.
The project will provide a comprehensive methodology for simulating sources of degradation and variability in devices based on new materials, along with a reference database for identifying those sources from a given measured signal. Both of these will be invaluable resources for the research community and design engineers working on the characterization and optimization of current and future devices. The details of materials and device design optimization resulting from the project’s study of degradation and reliability will offer design guidelines directly accessible to design engineers for prototype development, and ultimately to nanoelectronic forges for device manufacture. A key result of the project will be a report drawing together all the project components as a comprehensive strategy for balancing the performance demands and reliability/degradation standards for next generation nanoelectronic devices based on new materials. This will be an important reference document for any efforts within the general nanoelectronics industry towards production.
At present, global efforts in modelling and experimental characterization of sources of degradation and poor reliability are led by European groups, several present within the MORDRED project – with particular strength in the study of relevant new materials. In order to harness this capability, and particularly their strong links to the European nanoelectronics industry, it is critical that we address current industrial concerns and provide a reliable strategy for future device design