Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies

Description

Overall objective: to enhance advanced CMOS RF and logic capability through the use of III-V heterostructure nanowires monolithically integrated on a silicon platform. INSIGHT will focus on: -Development and evaluation of the performance of silicon based, 94 GHz III-V nanowire MOSFET low-noise amplifiers. The technology opens a path for cost reduction of key mm-wave components for high bandwidth wireless applications. -Development of III-V nanowire MOSFETs on Si with breakdown voltage of 6 V, and evaluation of their performance in millimeter wave (90 GHz) power amplifier circuits. These devices will increase output power available from Si CMOS compatible mm-wave technologies with benefits for transceiver range and sensitivity. -Realisation of basic building blocks for future RF-circuits including mixers, Voltage-Controlled Oscillators, and frequency dividers for prescalers using silicon based III-V nanowire MOSFETS. -Development of science and technology for all-III-V nanowire CMOS on silicon targeting future technology nodes for 10 nm and below. This will be validated by the implementation and dynamic characterisation of a flip-flop as demonstration of the co-integration of III-V n- and p-type nanowire MOSFETs. INSIGHT is a strong consortium consisting of 7 partners with complimentary and well-documented experience in III-V MOS technology and millimeter-wave circuit design and implementation. Our main outcomes include : a)Technology toolbox including, materials, processes and integration for III-V n- and p-channel MOSFETs on a silicon platform, b) III-V nanowire MOSFET RF-transistor technology, c) Circuit design library, d) Circuit demonstrators with a clear technology path towards higher TRLs and commercialization. Our vision is to use III-V nanowire CMOS technology for millimeter-wave applications in a System-on-Chip approach, combining RF- and logic on one Si chip. Additionally, applications for logic at the 10 nm node and beyond are foreseen.

KEY DATES
  • Status
  • Completed
  • Project Launch
  • 01 December 2015
  • Project completed
  • 30 November 2018
×